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The following ARM cores are synthesizable.  It is likely that all future ARM cores will also be synthesizable.  They are delivered as VHDL or Verilog and designated by a ‘-S’ at the end of the part number:

All synthesizable ARM cores are rising edge clocked throughout and provide debug access via JTAG.  However the JTAG standard requires that the JTAG signals are synchronized to TCK and that TDO is generated on the falling edge of TCK.  Therefore ARM publish a 'TCK synchronizer' circuit which can be used to interface IEEE standard JTAG with a core operating in a single clock rising edge domain.

The white paper below describes the issue in more detail.

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Technical Documents